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| * othe r brand s an d name s ar e th e propert y o f thei r respectiv e owners. informatio n i n thi s documen t i s provide d i n connectio n wit h inte l products . inte l assume s n o liabilit y whatsoever , includin g infringemen t o f an y paten t or copyright , fo r sal e an d us e o f inte l product s excep t a s provide d i n intel s term s an d condition s o f sal e fo r suc h products . inte l retain s th e righ t t o make change s t o thes e specification s a t an y time , withou t notice . microcompute r product s ma y hav e mino r variation s t o thi s specificatio n know n a s errata. july, 2004 copyrigh t ? inte l corporation , 2004 orde r number : 272433-006 80c186eb/80c188e b an d 80l186eb/80l188eb 16-bi t high-integratio n embedde d processors ful l stati c operation tru e cmo s input s an d outputs integrate d featur e set low-powe r stati c cp u core tw o independen t uart s eac h with a n integra l bau d rat e generator tw o 8-bi t multiplexe d i/ o ports programmabl e interrup t controller thre e programmabl e 16-bit timer/counters cloc k generator te n programmabl e chi p select s with integra l wait-stat e generator memor y refres h contro l unit syste m leve l testin g suppor t (once mode) direc t addressin g capabilit y t o 1 mbyte memor y an d 6 4 kbyt e i/o spee d version s availabl e (5v): 2 5 mh z (80c186eb25/80c188eb25) 2 0 mh z (80c186eb20/80c188eb20) 1 3 mh z (80c186eb13/80c188eb13) availabl e i n extende d temperature rang e ( - 40 c t o + 85 c) spee d version s availabl e (3v): 1 6 mh z (80l186eb16/80l188eb16) 1 3 mh z (80l186eb13/80l188eb13) low-powe r operatin g modes: idl e mod e freeze s cp u clock s but keep s peripheral s active powerdow n mod e freeze s all interna l clocks support s 80c18 7 numeri c coprocessor interfac e (80c186e b plc c only) availabl e in: 80-pi n qua d fla t pac k (qfp) 84-pi n plasti c leade d chi p carrier (plcc) 80-pi n shrin k qua d fla t pac k (sqfp) th e 80c186e b i s a secon d generatio n chmo s high-integratio n microprocessor . i t ha s feature s tha t ar e new t o th e 80c18 6 famil y an d includ e a stati c cp u core , a n enhance d chi p selec t decod e unit , tw o independent seria l channels , i/ o ports , an d th e capabilit y o f idl e o r powerdow n lo w powe r modes. 27243 3 C 1
80c186eb/80c188eb and 80l186eb/80l188eb 16-bit high-integration embedded processors contents page introduction 4 core architecture 4 bus interface unit 4 clock generator 4 80c186ec peripheral architecture 5 interrupt control unit 5 timer/counter unit 5 serial communications unit 7 chip-select unit 7 i/o port unit 7 refresh control unit 7 power management unit 7 80c187 interface (80c186eb only) 7 once test mode 7 package information 8 prefix identification 8 pin descriptions 8 80c186eb pinout 14 package thermal specifications 22 electrical specifications 23 absolute maximum ratings 23 contents page recommended connections 23 dc specifications 24 i cc versus frequency and voltage 27 pdtmr pin delay calculation 27 ac specifications 28 ac characteristicse80c186eb25 28 ac characteristicse80c186eb20/13 30 ac characteristicse80l186eb16 32 relative timings 36 serial port mode 0 timings 37 ac test conditions 38 ac timing waveforms 38 derating curves 41 reset 42 bus cycle waveforms 45 execution timings 52 instruction set summary 53 errata 59 revision history 59 2 80c186eb/80c188eb, 80l186eb/80l188eb 272433 2 note: pin names in parentheses apply to the 80c188eb/80l188eb figure 1. 80c186eb/80c188eb block diagram 3 80c186eb/80c188eb, 80l186eb/80l188eb introduction unless specifically noted, all references to the 80c186eb apply to the 80c188eb, 80l186eb, and 80l188eb. references to pins that differ between the 80c186eb/80l186eb and the 80c188eb/ 80l188eb are given in parentheses. the ``l'' in the part number denotes low voltage operation. physi- cally and functionally, the ``c'' and ``l'' devices are identical. the 80c186eb is the first product in a new genera- tion of low-power, high-integration microprocessors. it enhances the existing 186 family by offering new features and new operating modes. the 80c186eb is object code compatible with the 80c186xl/ 80c188xl microprocessors. the 80l186eb is the 3v version of the 80c186eb. the 80l186eb is functionally identical to the 80c186eb embedded processor. current 80c186eb users can easily upgrade their designs to use the 80l186eb and benefit from the reduced power consumption inherent in 3v operation. the feature set of the 80c186eb meets the needs of low power, space critical applications. low-power applications benefit from the static design of the cpu core and the integrated peripherals as well as low voltage operation. minimum current consump- tion is achieved by providing a powerdown mode that halts operation of the device, and freezes the clock circuits. peripheral design enhancements en- sure that non-initialized peripherals consume little current. space critical applications benefit from the inte- gration of commonly used system peripherals. two serial channels are provided for services such as diagnostics, inter-processor communication, modem interface, terminal display interface, and many oth- ers. a flexible chip select unit simplifies memory and peripheral interfacing. the interrupt unit provides sources for up to 129 external interrupts and will pri- oritize these interrupts with those generated from the on-chip peripherals. three general purpose tim- er/counters and sixteen multiplexed i/o port pins round out the feature set of the 80c186eb. figure 1 shows a block diagram of the 80c186eb/ 80c188eb. the execution unit (eu) is an enhanced 8086 cpu core that includes: dedicated hardware to speed up effective address calculations, enhance execution speed for multiple-bit shift and rotate in- structions and for multiply and divide instructions, string move instructions that operate at full bus bandwidth, ten new instruction, and fully static oper- ation. the bus interface unit (biu) is the same as that found on the original 186 family products, ex- cept the queue status mode has been deleted and buffer interface control has been changed to ease system design timings. an independent internal bus is used to allow communication between the biu and internal peripherals. core architecture bus interface unit the 80c186eb core incorporates a bus controller that generates local bus control signals. in addition, it employs a hold/hlda protocol to share the local bus with other bus masters. the bus controller is responsible for generating 20 bits of address, read and write strobes, bus cycle status information, and data (for write operations) in- formation. it is also responsible for reading data off the local bus during a read operation. a ready in- put pin is provided to extend a bus cycle beyond the minimum four states (clocks). the local bus controller also generates two control signals (den and dt/r ) when interfacing to exter- nal transceiver chips. (both den and dt/r are available on the plcc devices, only den is avail- able on the qfp and sqfp devices.) this capability allows the addition of transceivers for simple buffer- ing of the multiplexed address/data bus. clock generator the processor provides an on-chip clock generator for both internal and external clock generation. the clock generator features a crystal oscillator, a divide- by-two counter, and two low-power operating modes. the oscillator circuit is designed to be used with ei- ther a parallel resonant fundamental or third-over- tone mode crystal network. alternatively, the oscilla- tor circuit may be driven from an external clock source. figure 2 shows the various operating modes of the oscillator circuit. the crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide-by-two counter. this counter is used to drive all internal phase clocks and the exter- nal clkout signal. clkout is a 50% duty cycle processor clock and can be used to drive other sys- tem components. all ac timings are referenced to clkout. 4 80c186eb/80c188eb, 80l186eb/80l188eb 272433 3 (a) crystal connection note: the l 1 c 1 network is only required when using a third- overtone crystal. 272433 4 (b) clock connection figure 2. clock configurations the following parameters are recommended when choosing a crystal: temperature range: application specific esr (equivalent series resistance): 40 x max c0 (shunt capacitance of crystal): 7.0 pf max c l (load capacitance): 20 pf g 2pf drive level: 1 mw max 80c186eb peripheral architecture the 80c186eb has integrated several common sys- tem peripherals with a cpu core to create a com- pact, yet powerful system. the integrated peripher- als are designed to be flexible and provide logical interconnections between supporting units (e.g., the interrupt control unit supports interrupt requests from the timer/counters or serial channels). the list of integrated peripherals includes: # 7-input interrupt control unit # 3-channel timer/counter unit # 2-channel serial communications unit # 10-output chip-select unit # i/o port unit # refresh control unit # power management unit the registers associated with each integrated peri- heral are contained within a 128 x 16 register file called the peripheral control block (pcb). the pcb can be located in either memory or i/o space on any 256 byte address boundary. figure 3 provides a list of the registers associated with the pcb. the register bit summary at the end of this specification individually lists all of the regis- ters and identifies each of their programming attri- butes. interrupt control unit the 80c186eb can receive interrupts from a num- ber of sources, both internal and external. the inter- rupt control unit serves to merge these requests on a priority basis, for individual service by the cpu. each interrupt source can be independently masked by the interrupt control unit (icu) or all interrupts can be globally masked by the cpu. internal interrupt sources include the timers and se- rial channel 0. external interrupt sources come from the five input pins int4:0. the nmi interrupt pin is not controlled by the icu and is passed directly to the cpu. although the timer and serial channel each have only one request input to the icu, sepa- rate vector types are generated to service individual interrupts within the timer and serial channel units. timer/counter unit the 80c186eb timer/counter unit (tcu) provides three 16-bit programmable timers. two of these are highly flexible and are connected to external pins for control or clocking. a third timer is not connected to any external pins and can only be clocked internally. however, it can be used to clock the other two timer channels. the tcu can be used to count external events, time external events, generate non-repeti- tive waveforms, generate timed interrupts. etc. 5 80c186eb/80c188eb, 80l186eb/80l188eb pcb function offset 00h reserved 02h end of interrupt 04h poll 06h poll status 08h interrupt mask 0ah priority mask 0ch in-service 0eh interrupt request 10h interrupt status 12h timer control 14h serial control 16h int4 control 18h int0 control 1ah int1 control 1ch int2 control 1eh int3 control 20h reserved 22h reserved 24h reserved 26h reserved 28h reserved 2ah reserved 2ch reserved 2eh reserved 30h timer0 count 32h timer0 compare a 34h timer0 compare b 36h timer0 control 38h timer1 count 3ah timer1 compare a 3ch timer1 compare b 3eh timer1 control pcb function offset 40h timer2 count 42h timer2 compare 44h reserved 46h timer2 control 48h reserved 4ah reserved 4ch reserved 4eh reserved 50h port 1 direction 52h port 1 pin 54h port 1 control 56h port 1 latch 58h port 2 direction 5ah port 2 pin 5ch port 2 control 5eh port 2 latch 60h serial0 baud 62h serial0 count 64h serial0 control 66h serial0 status 68h serial0 rbuf 6ah serial0 tbuf 6ch reserved 6eh reserved 70h serial1 baud 72h serial1 count 74h serial1 control 76h serial1 status 78h serial1 rbuf 7ah serial1 tbuf 7ch reserved 7eh reserved pcb function offset 80h gcs0 start 82h gcs0 stop 84h gcs1 start 86h gcs1 stop 88h gcs2 start 8ah gcs2 stop 8ch gcs3 start 8eh gcs3 stop 90h gcs4 start 92h gcs4 stop 94h gcs5 start 96h gcs5 stop 98h gcs6 start 9ah gcs6 stop 9ch gcs7 start 9eh gcs7 stop a0h lcs start a2h lcs stop a4h ucs start a6h ucs stop a8h relocation aah reserved ach reserved aeh reserved b0h refresh base b2h refresh time b4h refresh control b6h reserved b8h power control bah reserved bch step id beh reserved pcb function offset c0h reserved c2h reserved c4h reserved c6h reserved c8h reserved cah reserved cch reserved ceh reserved d0h reserved d2h reserved d4h reserved d6h reserved d8h reserved dah reserved dch reserved deh reserved e0h reserved e2h reserved e4h reserved e6h reserved e8h reserved eah reserved ech reserved eeh reserved f0h reserved f2h reserved f4h reserved f6h reserved f8h reserved fah reserved fch reserved feh reserved figure 3. peripheral control block registers 6 80c186eb/80c188eb, 80l186eb/80l188eb serial communications unit the serial control unit (scu) of the 80c186eb con- tains two independent channels. each channel is identical in operation except that only channel 0 is supported by the integrated interrupt controller (channel 1 has an external interrupt pin). each channel has its own baud rate generator that is in- dependent of the timer/counter unit, and can be internally or externally clocked at up to one half the 80c186eb operating frequency. independent baud rate generators are provided for each of the serial channels. for the asynchronous modes, the generator supplies an 8x baud clock to both the receive and transmit register logic. a 1x baud clock is provided in the synchronous mode. chip-select unit the 80c186eb chip-select unit (csu) integrates logic which provides up to ten programmable chip- selects to access both memories and peripherals. in addition, each chip-select can be programmed to automatically insert additional clocks (wait-states) into the current bus cycle and automatically termi- nate a bus cycle independent of the condition of the ready input pin. i/o port unit the i/o port unit (ipu) on the 80c186eb supports two 8-bit channels of input, output, or input/output operation. port 1 is multiplexed with the chip select pins and is output only. most of port 2 is multiplexed with the serial channel pins. port 2 pins are limited to either an output or input function depending on the operation of the serial pin it is multiplexed with. refresh control unit the refresh control unit (rcu) automatically gen- erates a periodic memory read bus cycle to keep dynamic or pseudo-static memory refreshed. a 9-bit counter controls the number of clocks between re- fresh requests. a 12-bit address generator is maintained by the rcu and is presented on the a12:1 address lines during the refresh bus cycle. address bits a19:13 are pro- grammable to allow the refresh address block to be located on any 8 kbyte boundary. power management unit the 80c186eb power management unit (pmu) is provided to control the power consumption of the device. the pmu provides three power modes: ac- tive, idle, and powerdown. active mode indicates that all units on the 80c186eb are functional and the device consumes maximum power (depending on the level of periph- eral operation). idle mode freezes the clocks of the execution and bus units at a logic zero state (all peripherals continue to operate normally). the powerdown mode freezes all internal clocks at a logic zero level and disables the crystal oscillator. all internal registers hold their values provided v cc is maintained. current consumption is reduced to just transistor junction leakage. 80c187 interface (80c186eb only) the 80c186eb (plcc package only) supports the direct connection of the 80c187 numerics coproc- essor. once test mode to facilitate testing and inspection of devices when fixed into a target system, the 80c186eb has a test mode available which forces all output and input/ output pins to be placed in the high-impedance state. once stands for ``on circuit emulation''. the once mode is selected by forcing the a19/once pin low (0) during a processor reset (this pin is weakly held to a high (1) level) while resin is ac- tive. 7 80c186eb/80c188eb , 80l186eb/80l188eb packag e information thi s sectio n describe s th e pins , pinouts , an d thermal characteristic s fo r th e 80c186e b i n th e plastic leade d chi p carrie r (plcc ) package , shrin k quad fla t pac k (sqfp) , an d qua d fla t pac k (qfp ) pack- age . fo r complet e packag e specification s an d infor- mation , se e th e inte l packagin g outline s an d dimen- sion s guid e (orde r number : 231369). prefi x identification wit h th e extende d temperatur e range , operational characteristic s ar e guarantee d ove r th e temperature rang e correspondin g to - 40 c to + 85 c ambient. packag e type s ar e identifie d b y a two-lette r prefi x to th e par t number . th e prefixe s ar e liste d i n tabl e 1. tabl e 1 . prefi x identification prefi x note packag e temperature typ e type x x plc c extended x x qf p (eiaj ) extended x x 2 sqf p extended/commercial x 2 plc c commercial x 2 qf p (eiaj ) commercial note : 2 . th e 5 v 2 5 mh z an d 3 v 1 6 mh z version s ar e onl y avail- abl e i n commercia l temperatur e rang e correspondin g to 0 c to a 70 c ambient. pi n descriptions eac h pi n o r logica l se t o f pin s i s describe d i n table 3 . ther e ar e thre e column s fo r eac h entr y i n th e pin descriptio n table. the pi n name colum n contain s a mnemoni c that describe s th e pi n function . negatio n o f th e signal nam e (fo r example , resin ) denote s a signa l tha t is activ e low. the pi n type colum n contain s tw o kind s o f informa- tion . th e firs t symbo l indicate s whethe r a pi n i s pow- e r (p) , groun d (g) , inpu t onl y (i) , outpu t onl y (o ) or input/outpu t (i/o) . som e pin s hav e multiplexed function s (fo r example , a19/s6) . additiona l symbols indicat e additiona l characteristic s fo r eac h pin . table 2 list s al l th e possibl e symbol s fo r thi s column. the inpu t type colum n indicate s th e typ e o f input (asynchronou s o r synchronous). asynchronou s pin s requir e tha t setu p an d hol d times b e me t onl y i n orde r t o guarantee recognition a t a particula r cloc k edge . synchronou s pin s requir e that setu p an d hol d time s b e me t t o guarante e proper operation. fo r example , missin g th e setu p o r hold tim e fo r th e srd y pi n ( a synchronou s input ) wil l re- sul t i n a syste m failur e o r lockup . inpu t pin s ma y also b e edge - o r level-sensitive . th e possibl e character- istic s fo r inpu t pin s ar e s(e) , s(l) , a(e ) an d a(l). the outpu t states colum n indicate s th e output stat e a s a functio n o f th e devic e operatin g mode. outpu t state s ar e dependen t upo n th e curren t activi- t y o f th e processor . ther e ar e fou r operational state s tha t ar e differen t fro m regula r operation : bus hold , reset , idl e mod e an d powerdow n mode . ap- propriat e characteristic s fo r thes e state s ar e als o in- dicate d i n thi s column , wit h th e legen d fo r al l possi- bl e characteristic s i n tabl e 2. the pi n description colum n contain s a tex t de- scriptio n o f eac h pin. a s a n example , conside r ad15.0 . i/ o signifie s the pin s ar e bidirectional . s(l ) signifie s tha t th e input functio n i s synchronou s an d level-sensitive . h(z) signifie s that , a s outputs , th e pin s ar e high-imped- anc e upo n acknowledgemen t o f bu s hold . r(z ) sig- nifie s tha t th e pin s floa t durin g reset . p(x ) signifies tha t th e pin s retai n thei r state s durin g powerdown mode. 8 1. to address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x". 1 1 1, 1, 1, 80c186eb/80c188eb, 80l186eb/80l188eb table 2. pin description nomenclature symbol description p power pin (apply a v cc voltage) g ground (connect to v ss ) i input only pin o output only pin i/o input/output pin s(e) synchronous, edge sensitive s(l) synchronous, level sensitive a(e) asynchronous, edge sensitive a(l) asynchronous, level sensitive h(1) output driven to v cc during bus hold h(0) output driven to v ss during bus hold h(z) output floats during bus hold h(q) output remains active during bus hold h(x) output retains current state during bus hold r(wh) output weakly held at v cc during reset r(1) output driven to v cc during reset r(0) output driven to v ss during reset r(z) output floats during reset r(q) output remains active during reset r(x) output retains current state during reset i(1) output driven to v cc during idle mode i(0) output driven to v ss during idle mode i(z) output floats during idle mode i(q) output remains active during idle mode i(x) output retains current state during idle mode p(1) output driven to v cc during powerdown mode p(0) output driven to v ss during powerdown mode p(z) output floats during powerdown mode p(q) output remains active during powerdown mode p(x) output retains current state during powerdown mode 9 80c186eb/80c188eb, 80l186eb/80l188eb table 3. pin descriptions pin pin input output description name type type states v cc pe e power connections consist of four pins which must be shorted externally to a v cc board plane. v ss ge e ground connections consist of six pins which must be shorted externally to a v ss board plane. clkin i a(e) e clock input is an input for an external clock. an external oscillator operating at two times the required processor operating frequency can be connected to clkin. for crystal operation, clkin (along with oscout) are the crystal connections to an internal pierce oscillator. oscout o e h(q) oscillator output is only used when using a crystal to generate the external clock. oscout (along with clkin) r(q) are the crystal connections to an internal pierce oscillator. p(q) this pin is not to be used as 2x clock output for non-crystal applications (i.e., this pin is n.c. for non-crystal applications). oscout does not float in once mode. clkout o e h(q) clock output provides a timing reference for inputs and outputs of the processor, and is one-half the input clock r(q) (clkin) frequency. clkout has a 50% duty cycle and p(q) transistions every falling edge of clkin. resin i a(l) e reset in causes the processor to immediately terminate any bus cycle in progress and assume an initialized state. all pins will be driven to a known state, and resout will also be driven active. the rising edge (low-to-high) transition synchronizes clkout with clkin before the processor begins fetching opcodes at memory location 0ffff0h. resout o e h(0) reset output that indicates the processor is currently in the reset state. resout will remain active as long as resin r(1) remains active. p(0) pdtmr i/o a(l) h(wh) power-down timer pin (normally connected to an external capacitor) that determines the amount of time the processor r(z) waits after an exit from power down before resuming normal p(1) operation. the duration of time required will depend on the startup characteristics of the crystal oscillator. nmi i a(e) e non-maskable interrupt input causes a type-2 interrupt to be serviced by the cpu. nmi is latched internally. test /busy i a(e) e test is used during the execution of the wait instruction to suspend cpu operation until the pin is sampled active (test ) (low). test is alternately known as busy when interfacing with an 80c187 numerics coprocessor (80c186eb only). ad15:0 i/o s(l) h(z) these pins provide a multiplexed address and data bus. during the address phase of the bus cycle, address bits 0 (ad7:0) r(z) through 15 (0 through 7 on the 80c188eb) are presented on p(x) the bus and can be latched using ale. 8- or 16-bit data information is transferred during the data phase of the bus cycle. note: pin names in parentheses apply to the 80c188eb/80l188eb. 10 80c186eb/80c188eb, 80l186eb/80l188eb table 3. pin descriptions (continued) pin pin input output description name type type states a18:16 i/o a(l) h(z) these pins provide multiplexed address during the address phase of the bus cycle. address bits 16 through 19 are presented a19/once r(wh) on these pins and can be latched using ale. these pins are (a15:a8) p(x) driven to a logic 0 during the data phase of the bus cycle. on the (a18:16) 80c188eb, a15 a8 provide valid address information for the (a19/once) entire bus cycle. during a processor reset (resin active), a19/ once is used to enable once mode. a18:16 must not be driven low during reset or improper operation may result. s2:0 o e h(z) bus cycle status are encoded on these pins to provide bus transaction information. s2:0 are encoded as follows: r(z) p(1) s2 s1 s0 bus cycle initiated 0 0 0 interrupt acknowledge 0 0 1 read i/o 0 1 0 write i/o 0 1 1 processor halt 1 0 0 queue instruction fetch 1 0 1 read memory 1 1 0 write memory 1 1 1 passive (no bus activity) ale o e h(0) address latch enable output is used to strobe address information into a transparent type latch during the address phase r(0) of the bus cycle. p(0) bhe o e h(z) byte high enable output to indicate that the bus cycle in progress is transferring data over the upper half of the data bus. bhe and (rfsh ) r(z) a0 have the following logical encoding p(x) a0 bhe encoding (for the 80c186eb/80l186eb only) 0 0 word transfer 0 1 even byte transfer 1 0 odd byte transfer 1 1 refresh operation on the 80c188eb/80l188eb, rfsh is asserted low to indicate a refresh bus cycle. rd o e h(z) read output signals that the accessed memory or i/o device must drive data information onto the data bus. r(z) p(1) wr o e h(z) write output signals that data available on the data bus are to be written into the accessed memory or i/o device. r(z) p(1) ready i a(l) e ready input to signal the completion of a bus cycle. ready must be active to terminate any bus cycle, unless it is ignored by s(l) correctly programming the chip-select unit. den o e h(z) data enable output to control the enable of bi-directional transceivers in a buffered system. den is active only when data is r(z) to be transferred on the bus. p(1) note: pin names in parentheses apply to the 80c188eb/80l188eb. 11 80c186eb/80c188eb, 80l186eb/80l188eb table 3. pin descriptions (continued) pin pin input output description name type type states dt/r o e h(z) data transmit/receive output controls the direction of a bi-directional buffer in a buffered system. dt/r is only r(z) available for the plcc package. p(x) lock o e h(z) lock output indicates that the bus cycle in progress is not to be interrupted. the processor will not service other bus r(wh) requests (such as hold) while lock is active. this pin is p(1) configured as a weakly held high input while resin is active and must not be driven low. hold i a(l) e hold request input to signal that an external bus master wishes to gain control of the local bus. the processor will relinquish control of the local bus between instruction boundaries not conditioned by a lock prefix. hlda o e h(1) hold acknowledge output to indicate that the processor has relinquished control of the local bus. when hlda is r(0) asserted, the processor will (or has) floated its data bus p(0) and control signals allowing another bus master to drive the signals directly. ncs o e h(1) numerics coprocessor select output is generated when accessing a numerics coprocessor. ncs is not provided on (n.c.) r(1) the qfp or sqfp packages. this signal does not exist on p(1) the 80c188eb/80l188eb. error i a(l) e error input that indicates the last numerics coprocessor operation resulted in an exception condition. an interrupt (n.c.) type 16 is generated if error is sampled active at the beginning of a numerics operation. error is not provided on the qfp or sqfp packages. this signal does not exist on the 80c188eb/80l188eb. pereq i a(l) e coprocessor request signals that a data transfer between an external numerics coprocessor and memory is (n.c.) pending. pereq is not provided on the qfp or sqfp packages. this signal does not exist on the 80c188eb/ 80l188eb. ucs o e h(1) upper chip select will go active whenever the address of a memory or i/o bus cycle is within the address limitations r(1) programmed by the user. after reset, ucs is configured to p(1) be active for memory accesses between 0ffc00h and 0fffffh. lcs o e h(1) lower chip select will go active whenever the address of a memory bus cycle is within the address limitations r(1) programmed by the user. lcs is inactive after a reset. p(1) p1.0/gcs0 o e h(x)/h(1) these pins provide a multiplexed function. if enabled, each pin can provide a generic chip select output which will go p1.1/gcs1 r(1) active whenever the address of a memory or i/o bus cycle p1.2/gcs2 p(x)/p(1) is within the address limitations programmed by the user. p1.3/gcs3 when not programmed as a chip-select, each pin may be p1.4/gcs4 used as a general purpose output port. as an output port p1.5/gcs5 pin, the value of the pin can be read internally. p1.6/gcs6 p1.7/gcs7 note: pin names in parentheses apply to the 80c188eb/80l188eb. 12 80c186eb/80c188eb, 80l186eb/80l188eb table 3. pin descriptions (continued) pin pin input output description name type type states t0out o e h(q) timer output pins can be programmed to provide a single clock or continuous waveform generation, t1out r(1) depending on the timer mode selected. p(q) t0in i a(l) e timer input is used either as clock or control signals, depending on the timer mode selected. t1in a(e) int0 i a(e,l) e maskable interrupt input will cause a vector to a specific type interrupt routine. to allow interrupt int1 expansion, int0 and/or int1 can be used with int4 inta0 and inta1 to interface with an external slave controller. int2/inta0 i/o a(e,l) h(1) these pins provide a multiplexed function. as inputs, they provide a maskable interrupt that will cause int3/inta1 r(z) the cpu to vector to a specific type interrupt routine. p(1) as outputs, each is programmatically controlled to provide an interrupt acknowledge handshake signal to allow interrupt expansion. p2.7 i/o a(l) h(x) bi-directional, open-drain port pins. p2.6 r(z) p(x) ctso i a(l) e clear-to-send input is used to prevent the transmission of serial data on their respective txd p2.4/cts1 signal pin. cts1 is multiplexed with an input only port function. txd0 o e h(x)/h(q) transmit data output provides serial data information. txd1 is multiplexed with an output only p2.1/txd1 r(1) port function. during synchronous serial p(x)/p(q) communications, txd will function as a clock output. rxd0 i/o a(l) r(z) receive data input accepts serial data information. rxd1 is multiplexed with an input only port function. p2.0/rxd1 h(q) during synchronous serial communications, rxd is p(x) bi-directional and will become an output for transmission or data (txd becomes the clock). p2.5/bclk0 i a(l)/a(e) e baud clock input can be used as an alternate clock source for each of the integrated serial channels. p2.2/bclk1 bclkx is multiplexed with an input only port function, and cannot exceed a clock rate greater than one-half the operating frequency of the processor. p2.3/sint1 o e h(x)/h(q) serial interrupt output will go active to indicate serial channel 1 requires service. sint1 is r(0) multiplexed with an output only port function. p(x)/p(x) note: pin names in parentheses apply to the 80c188eb/80l188eb. 13 80c186eb/80c188eb, 80l186eb/80l188eb 80c186eb pinout tables 4 and 5 list the 80c186eb/80c188eb pin names with package location for the 84-pin plastic leaded chip carrier (plcc) component. figure 5 depicts the complete 80c186eb/80c188eb pinout (plcc package) as viewed from the top side of the component (i.e., contacts facing down). tables 6 and 7 list the 80c186eb/80c188eb pin names with package location for the 80-pin quad flat pack (qfp) component. figure 6 depicts the complete 80c186eb/80c188eb (qfp package) as viewed from the top side of the component (i.e., con- tacts facing down). tables 8 and 9 list the 80186eb/80188eb pin names with package location for the 80-pin shrink quad flat pack (sqfp) component. figure 7 depicts the complete 80c186eb/80c188eb (sqfp pack- age) as viewed from the top side of the component (i.e., contacts facing down). table 4. plcc pin names with package location address/data bus name location ad0 61 ad1 66 ad2 68 ad3 70 ad4 72 ad5 74 ad6 76 ad7 78 ad8 (a8) 62 ad9 (a9) 67 ad10 (a10) 69 ad11 (a11) 71 ad12 (a12) 73 ad13 (a13) 75 ad14 (a14) 77 ad15 (a15) 79 a16 80 a17 81 a18 82 a19/once 83 bus control name location ale 6 bhe (rfsh )7 s0 10 s1 9 s2 8 rd 4 wr 5 ready 18 den 11 dt/r 16 lock 15 hold 13 hlda 12 power name location v ss 2, 22, 43 63, 65, 84 v cc 1, 23 42, 64 processor control name location resin 37 resout 38 clkin 41 oscout 40 clkout 44 test /busy 14 ncs (n.c.) 60 pereq (n.c.) 39 error (n.c.) 3 pdtmr 36 nmi 17 int0 31 int1 32 int2/inta0 33 int3/inta1 34 int4 35 i/o name location ucs 30 lcs 29 p1.0/gcs0 28 p1.1/gcs1 27 p1.2/gcs2 26 p1.3/gcs3 25 p1.4/gcs4 24 p1.5/gcs5 21 p1.6/gcs6 20 p1.7/gcs7 19 t0out 45 t0in 46 t1out 47 t1in 48 rxd0 53 txd0 52 p2.5/bclk0 54 cts0 51 p2.0/rxd1 57 p2.1/txd1 58 p2.2/bclk1 59 p2.3/sint1 55 p2.4/cts1 56 p2.6 50 p2.7 49 note: pin names in parentheses apply to the 80c188eb/80l188eb. 14 80c186eb/80c188eb, 80l186eb/80l188eb table 5. plcc package locations with pin name location name 1v cc 2v ss 3 error (n.c.) 4rd 5wr 6 ale 7 bhe (rfsh ) 8s2 9s1 10 s0 11 den 12 hlda 13 hold 14 test /busy 15 lock 16 dt/r 17 nmi 18 ready 19 p1.7/gcs7 20 p1.6/gcs6 21 p1.5/gcs5 location name 22 v ss 23 v cc 24 p1.4/gcs4 25 p1.3/gcs3 26 p1.2/gcs2 27 p1.1/gcs1 28 p1.0/gcs0 29 lcs 30 ucs 31 int0 32 int1 33 int2/inta0 34 int3/inta1 35 int4 36 pdtmr 37 resin 38 resout 39 pereq (n.c.) 40 oscout 41 clkin 42 v cc location name 43 v ss 44 clkout 45 t0out 46 t0in 47 t1out 48 t1in 49 p2.7 50 p2.6 51 cts0 52 txd0 53 rxd0 54 p2.5/bclk0 55 p2.3/sint1 56 p2.4/cts1 57 p2.0/rxd1 58 p2.1/txd1 59 p2.2/bclk1 60 ncs (n.c.) 61 ad0 62 ad8 (a8) 63 v ss location name 64 v cc 65 v ss 66 ad1 67 ad9 (a9) 68 ad2 69 ad10 (a10) 70 ad3 71 ad11 (a11) 72 ad4 73 ad12 (a12) 74 ad5 75 ad13 (a13) 76 ad6 77 ad14 (a14) 78 ad7 79 ad15 (a15) 80 a16 81 a17 82 a18 83 a19/once 84 v ss note: pin names in parentheses apply to the 80c188eb/80l188eb. 15 80c186eb/80c188eb , 80l186eb/80l188eb 27243 3 C 5 note: thi s i s th e fp o numbe r locatio n (indicate d b y xs). pi n name s i n parenthese s appl y t o th e 80c188eb/80l188eb. figur e 4 . 84-pi n plasti c leade d chi p carrie r pinou t diagram 16 80c186eb/80c188eb, 80l186eb/80l188eb table 6. qfp pin name with package location address/data bus name location ad0 10 ad1 15 ad2 17 ad3 19 ad4 21 ad5 23 ad6 25 ad7 27 ad8 (a8) 11 ad9 (a9) 16 ad10 (a10) 18 ad11 (a11) 20 ad12 (a12) 22 ad13 (a13) 24 ad14 (a14) 26 ad15 (a15) 28 a16 29 a17 30 a18 31 a19/once 32 bus control name location ale 38 bhe (rfsh )39 s0 42 s1 41 s2 40 rd 36 wr 37 ready 49 den 43 lock 47 hold 45 hlda 44 power name location v ss 12, 14, 33 35, 53, 73 v cc 13, 34 54, 72 processor control name location resin 68 resout 69 clkin 71 oscout 70 clkout 74 test 46 pdtmr 67 nmi 48 int0 62 int1 63 int2/inta0 64 int3/inta1 65 int4 66 i/o name location ucs 61 lcs 60 p1.0/gcs0 59 p1.1/gcs1 58 p1.2/gcs2 57 p1.3/gcs3 56 p1.4/gcs4 55 p1.5/gcs5 52 p1.6/gcs6 51 p1.7/gcs7 50 t0out 75 t0in 76 t1out 77 t1in 78 rxd0 3 txd0 2 p2.5/bclk0 4 cts0 1 p2.0/rxd1 7 p2.1/txd1 8 p2.2/bclk1 9 p2.3/sint1 5 p2.4/cts1 6 p2.6 80 p2.7 79 note: pin names in parentheses apply to the 80c188eb/80l188eb. 17 80c186eb/80c188eb, 80l186eb/80l188eb table 7. qfp package location with pin names location name 1 cts0 2 txd0 3 rxd0 4 p2.5/bclk0 5 p2.3/sint1 6 p2.4/cts1 7 p2.0/rxd1 8 p2.1/txd1 9 p2.2/bclk1 10 ad0 11 ad8 (a8) 12 v ss 13 v cc 14 v ss 15 ad1 16 ad9 (a9) 17 ad2 18 ad10 (a10) 19 ad3 20 ad11 (a11) location name 21 ad4 22 ad12 (a12) 23 ad5 24 ad13 (a13) 25 ad6 26 ad14 (a14) 27 ad7 28 ad15 (a15) 29 a16 30 a17 31 a18 32 a19/once 33 v ss 34 v cc 35 v ss 36 rd 37 wr 38 ale 39 bhe (rfsh ) 40 s2 location name 41 s1 42 s0 43 den 44 hlda 45 hold 46 test 47 lock 48 nmi 49 ready 50 p1.7/gcs7 51 p1.6/gcs6 52 p1.5/gcs5 53 v ss 54 v cc 55 p1.4/gcs4 56 p1.3/gcs3 57 p1.2/gcs2 58 p1.1/gcs1 59 p1.0/gcs0 60 lcs location name 61 ucs 62 int0 63 int1 64 int2/inta0 65 int3/inta1 66 int4 67 pdtmr 68 resin 69 resout 70 oscout 71 clkin 72 v cc 73 v ss 74 clkout 75 t0out 76 t0in 77 t1out 78 t1in 79 p2.7 80 p2.6 note: pin names in parentheses apply to the 80c188eb/80l188eb. 18 80c186eb/80c188eb , 80l186eb/80l188eb 27243 3 C 6 note: thi s i s th e fp o numbe r locatio n (indicate d b y xs). pi n name s i n parenthese s appl y t o th e 80c188eb/80l188eb. figur e 5 . qua d fla t pac k pinou t diagram 19 80c186eb/80c188eb, 80l186eb/80l188eb table 8. sqfp pin functions with location ad bus ad0 47 ad1 52 ad2 54 ad3 56 ad4 58 ad5 60 ad6 62 ad7 64 ad8 (a8) 48 ad9 (a9) 53 ad10 (a10) 55 ad11 (a11) 57 ad12 (a12) 59 ad13 (a13) 61 ad14 (a14) 63 ad15 (a15) 65 a16 66 a17 67 a18 68 a19/once 69 bus control ale 75 bhe y (rfsh y )76 s0 y 79 s1 y 78 s2 y 77 rd y 73 wr y 74 ready 6 den y 80 lock y 4 hold 2 hlda 1 processor control resin y 25 resout 26 clkin 28 oscout 27 clkout 31 test y /busy 3 nmi 5 int0 19 int1 20 int2/inta0 y 21 int3/inta1 y 22 int4 23 pdtmr 24 power and ground v cc 11 v cc 29 v cc 50 v cc 71 v ss 10 v ss 30 v ss 49 v ss 51 v ss 70 v ss 72 i/o ucs y 18 lcs y 17 p1.0/gcs0 y 16 p1.1/gcs1 y 15 p1.2/gcs2 y 14 p1.3/gcs3 y 13 p1.4/gcs4 y 12 p1.5/gcs5 y 9 p1.6/gcs6 y 8 p1.7/gcs7 y 7 p2.0/rxd1 44 p2.1/txd1 45 p2.2/bclk1 46 p2.3/sint1 42 p2.4/cts1 y 43 p2.5/bclk0 41 p2.6 37 p2.7 36 cts0 y 38 txd0 39 rxd0 40 t0in 33 t1in 35 t0out 32 t1out 34 table 9. sqfp pin locations with pin names 1 hlda 2 hold 3 test y 4 lock y 5 nmi 6 ready 7 p1.7/gcs7 y 8 p1.6/gcs6 y 9 p1.5/gcs5 y 10 v ss 11 v cc 12 p1.4/gcs4 y 13 p1.3/gcs3 y 14 p1.2/gcs2 y 15 p1.1/gcs1 y 16 p1.0/gcs0 y 17 lcs y 18 ucs y 19 int0 20 int1 21 int1/inta0 y 22 int3/inta1 y 23 int4 24 pdtmr 25 resin y 26 resout 27 oscout 28 clkin 29 v cc 30 v ss 31 clkout 32 t0out 33 t0in 34 t1out 35 t1in 36 p2.7 37 p2.6 38 cts0 y 39 txd0 40 rxd0 41 p2.5/bclk0 42 p2.3/sint1 43 p2.4/cts1 y 44 p2.0/rxd1 45 p2.1/txd1 46 p2.2/bclk1 47 ad0 48 ad8 (a8) 49 v ss 50 v cc 51 v ss 52 ad1 53 ad9 (a9) 54 ad2 55 ad10 (a10) 56 ad3 57 ad11 (a11) 58 ad4 59 ad12 (a12) 60 ad5 61 ad13 (a13) 62 ad6 63 ad14 (a14) 64 ad7 65 ad15 (a15) 66 a16 67 a17 68 a18 69 a19/once 70 v ss 71 v cc 72 v ss 73 rd y 74 wr y 75 ale 76 bhe y (rfsh y ) 77 s2 y 78 s1 y 79 s0 y 80 den y note: pin names in parentheses apply to the 80c188eb/80l188eb. 20 80c186eb/80c188eb , 80l186eb/80l188eb 27243 3 C 7 note: xxxxxxxx c indicate s inte l fp o number. pi n name s i n parenthese s appl y t o th e 80c188eb/80l188eb. figur e 6 . sqf p package 21 80c186eb/80c188eb, 80l186eb/80l188eb package thermal specifications the 80c186eb/80l186eb is specified for operation when t c (the case temperature) is within the range of b 40 cto a 100 c (plcc package) or b 40 cto a 114 c (qfp package). t c may be measured in any environment to determine whether the proces- sor is within the specified operating range. the case temperature must be measured at the center of the top surface. t a (the ambient temperature) can be calculated from i ca (thermal resistance from the case to ambi- ent) with the following equation: t a e t c b p * i ca typical values for i ca at various airflows are given in table 10. p (the maximum power consumption, specified in watts) is calculated by using the maxi- mum icc as tabulated in the dc specifications and v cc of 5.5v. table 10. thermal resistance ( i ca ) at various airflows (in c/watt) airflow linear ft/min (m/sec) 0 200 400 600 800 1000 (0) (1.01) (2.03) (3.04) (4.06) (5.07) i ca (plcc) 30 24 21 19 17 16.5 i ca (qfp) 58 47 43 40 38 36 i ca (sqfp) 70 tbd tbd tbd tbd tbd 22 80c186eb/80c188eb, 80l186eb/80l188eb electrical specifications absolute maximum ratings storage temperature b 65 cto a 150 c case temp under bias b 65 cto a 120 c supply voltage with respect to v ss b 0.5v to a 6.5v voltage on other pins with respect to v ss b 0.5v to v cc a 0.5v notice: this data sheet contains preliminary infor- mation on new products in production. it is valid for the devices indicated in the revision history. the specifications are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. recommended connections power and ground connections must be made to multiple v cc and v ss pins. every 80c186eb-based circuit board should include separate power (v cc ) and ground (v ss ) planes. every v cc pin must be connected to the power plane, and every v ss pin must be connected to the ground plane. pins identi- fied as ``nc'' must not be connected in the system. liberal decoupling capacitance should be placed near the processor. the processor can cause tran- sient power surges when its output buffers tran- sition, particularly when connected to large capaci- tive loads. low inductance capacitors and interconnects are recommended for best high frequency electrical per- formance. inductance is reduced by placing the de- coupling capacitors as close as possible to the proc- essor v cc and v ss package pins. always connect any unused input to an appropriate signal level. in particular, unused interrupt inputs (int0:4) should be connected to v cc through a pull- up resistor (in the range of 50 k x ). leave any un- used output pin or any nc pin unconnected. 23 80c186eb/80c188eb, 80l186eb/80l188eb dc specifications (80c186eb/80c188eb) symbol parameter min max units notes v cc supply voltage 4.5 5.5 v v il input low voltage b 0.5 0.3 v cc v v ih input high voltage 0.7 v cc v cc a 0.5 v v ol output low voltage 0.45 v i ol e 3 ma (min) v oh output high voltage v cc b 0.5 v i oh eb 2 ma (min) v hyr input hysterisis on resin 0.50 v i li1 input leakage current for pins: g 15 m a0v s v in s v cc ad15:0 (ad7:0), ready, hold, resin , clkin, test , nmi, int4:0, t0in, t1in, rxd0, bclk0 , cts0 , rxd1, bclk1 , cts1 , p2.6, p2.7 i li2 input leakage current for pins: g 0.275 g 7ma0v s v in k v cc error , pereq i li3 input leakage current for pins: b 0.275 b 5.0 ma v in e 0.7 v cc (note 1) a19/once , a18:16, lock i lo output leakage current g 15 m a 0.45 s v out s v cc (note 2) i cc supply current cold (reset) 80c186eb25 115 ma (notes 3, 7) 80c186eb20 108 ma (note 3) 80c186eb13 73 ma (note 3) i id supply current idle 80c186eb25 91 ma (notes 4, 7) 80c186eb20 76 ma (note 4) 80c186eb13 48 ma (note 4) i pd supply current powerdown 80c186eb25 100 m a (notes 5, 7) 80c186eb20 100 m a (note 5) 80c186eb13 100 m a (note 5) c in input pin capacitance 0 15 pf t f e 1 mhz c out output pin capacitance 0 15 pf t f e 1 mhz (note 6) notes: 1. these pins have an internal pull-up device that is active while resin is low and once mode is not active. sourcing more current than specified (on any of these pins) may invoke a factory test mode. 2. tested by outputs being floated by invoking once mode or by asserting hold. 3. measured with the device in reset and at worst case frequency, v cc , and temperature with all outputs loaded as specified in ac test conditions, and all floating outputs driven to v cc or gnd. 4. measured with the device in halt (idle mode active) and at worst case frequency, v cc , and temperature with all outputs loaded as specified in ac test conditions, and all floating outputs driven to v cc or gnd. 5. measured with the device in halt (powerdown mode active) and at worst case frequency, v cc , and temperature with all outputs loaded as specified in ac test conditions, and all floating outputs driven to v cc or gnd. 6. output capacitance is the capacitive load of a floating output pin. 7. operating temperature for 25 mhz is 0 cto70 c, v cc e 5.0 g 10%. 24 80c186eb/80c188eb, 80l186eb/80l188eb dc specifications (80l186eb16) (operating temperature, 0 cto70 c) symbol parameter min max units notes v cc supply voltage 3.0 5.5 v v il input low voltage b 0.5 0.3 v cc v v ih input high voltage 0.7 v cc v cc a 0.5 v v ol output low voltage 0.45 v i ol e 1.6 ma (min) (note 1) v oh output high voltage v cc b 0.5 v i oh eb 1 ma (min) (note 1) v hyr input hysterisis on resin 0.50 v i li1 input leakage current for pins: g 15 m a0v s v in s v cc ad15:0 (ad7:0), ready, hold, resin , clkin, test , nmi, int4:0, t0in, t1in, rxd0, bclk0 , cts0 , rxd1, bclk1 , cts1 , sint1, p2.6, p2.7 i li2 input leakage current for pins: b 0.275 b 2mav in e 0.7 v cc (note 2) a19/once , a18:16, lock i lo output leakage current g 15 m a 0.45 s v out s v cc (note 3) i cc3 supply current (reset, 3.3v) 80l186eb16 54 ma (note 4) i id3 supply current idle (3.3v) 80l186eb16 38 ma (note 5) i pd3 supply current powerdown (3.3v) 80l186eb16 40 m a (note 6) c in input pin capacitance 0 15 pf t f e 1 mhz c out output pin capacitance 0 15 pf t f e 1 mhz (note 7) notes: 1. i ol and i oh measured at v cc e 3.0v. 2. these pins have an internal pull-up device that is active while resin is low and once mode is not active. sourcing more current than specified (on any of these pins) may invoke a factory test mode. 3. tested by outputs being floated by invoking once mode or by asserting hold. 4. measured with the device in reset and at worst case frequency, v cc , and temperature with all outputs loaded as specified in ac test conditions, and all floating outputs driven to v cc or gnd. 5. measured with the device in halt (idle mode active) and at worst case frequency, v cc , and temperature with all outputs loaded as specified in ac test conditions, and all floating outputs driven to v cc or gnd. 6. measured with the device in halt (powerdown mode active) and at worst case frequency, v cc , and temperature with all outputs loaded as specified in ac test conditions, and all floating outputs driven to v cc or gnd. 7. output capacitance is the capacitive load of a floating output pin. 25 80c186eb/80c188eb, 80l186eb/80l188eb i cc versus frequency and voltage the current (i cc ) consumption of the processor is essentially composed of two components; i pd and i ccs . i pd is the quiescent current that represents internal device leakage, and is measured with all inputs or floating outputs at gnd or v cc (no clock applied to the device). i pd is equal to the powerdown current and is typically less than 50 m a. i ccs is the switching current used to charge and discharge parasitic device capacitance when chang- ing logic levels. since i ccs is typically much greater than i pd ,i pd can often be ignored when calculating i cc . i ccs is related to the voltage and frequency at which the device is operating. it is given by the formula: power e v c i e v 2 c c dev c f . . . i e i cc e i ccs e v c c dev c f where: v e device operating voltage (v cc ) c dev e device capacitance f e device operating frequency i ccs e i cc e device current measuring c dev on a device like the 80c186eb would be difficult. instead, c dev is calculated using the above formula by measuring i cc at a known v cc and frequency (see table 11). using this c dev val- ue, i cc can be calculated at any voltage and fre- quency within the specified operating range. example: calculate the typical i cc when operating at 10 mhz, 4.8v. i cc e i ccs e 4.8 c 0.583 c 10 & 28 ma pdtmr pin delay calculation the pdtmr pin provides a delay between the as- sertion of nmi and the enabling of the internal clocks when exiting powerdown. a delay is required only when using the on-chip oscillator to allow the crystal or resonator circuit time to stabilize. note: the pdtmr pin function does not apply when resin is asserted (i.e., a device reset during pow- erdown is similar to a cold reset and resin must remain active until after the oscillator has stabi- lized). to calculate the value of capacitor required to pro- vide a desired delay, use the equation: 440 c t e c pd (5v, 25 c) where: t e desired delay in seconds c pd e capacitive load on pdtmr in mi- crofarads example: to get a delay of 300 m s, a capacitor value of c pd e 440 c (300 c 10 b 6 ) e 0.132 m fis required. round up to standard (available) capaci- tive values. note: the above equation applies to delay times greater than 10 m s and will compute the typical capaci- tance needed to achieve the desired delay. a delay variance of a 50% or b 25% can occur due to temperature, voltage, and device process ex- tremes. in general, higher v cc and/or lower tem- perature will decrease delay time, while lower v cc and/or higher temperature will increase delay time. table 11. device capacitance (c dev ) values parameter typ max units notes c dev (device in reset) 0.583 1.02 ma/v * mhz 1, 2 c dev (device in idle) 0.408 0.682 ma/v * mhz 1, 2 1. max c dev is calculated at b 40 c, all floating outputs driven to v cc or gnd, and all outputs loaded to 50 pf (including clkout and oscout). 2. typical c dev is calculated at 25 c with all outputs loaded to 50 pf except clkout and oscout, which are not loaded. 27 80c186eb/80c188eb, 80l186eb/80l188eb ac specifications ac characteristicse80c186eb25 symbol parameter 25 mhz units notes min max input clock t f clkin frequency 0 50 mhz 1 t c clkin period 20 % ns 1 t ch clkin high time 8 % ns 1, 2 t cl clkin low time 8 % ns 1, 2 t cr clkin rise time 1 7 ns 1, 3 t cf clkin fall time 1 7 ns 1, 3 output clock t cd clkin to clkout delay 0 16 ns 1, 4 t clkout period 2 * t c ns 1 t ph clkout high time (t/2) b 5 (t/2) a 5ns 1 t pl clkout low time (t/2) b 5 (t/2) a 5ns 1 t pr clkout rise time 1 6 ns 1, 5 t pf clkout fall time 1 6 ns 1, 5 output delays t chov1 ale, s2:0 , den , dt/r , bhe (rfsh ), lock , a19:16 3 17 ns 1, 4, 6, 7 t chov2 gcs0:7 , lcs , ucs , ncs ,rd ,wr 3 20 ns 1,4,6,8 t clov1 bhe (rfsh ), den , lock , resout, hlda, t0out, 3 17 ns 1, 4, 6 t1out, a19:16 t clov2 rd ,wr , gcs7:0 , lcs , ucs , ad15:0 (ad7:0, a15:8), 3 20 ns 1, 4, 6 ncs , inta1:0 , s2:0 t chof rd ,wr , bhe (rfsh ), dt/r , lock , s2:0 , a19:16 0 20 ns 1 t clof den , ad15:0 (ad7:0, a15:8) 0 20 ns 1 28 80c186eb/80c188eb, 80l186eb/80l188eb ac specifications ac characteristicse80c186eb25 (continued) symbol parameter 25 mhz units notes min max synchronous inputs t chis test , nmi, int4:0, bclk1:0, t1:0in, ready, cts1:0 , p2.6, p2.7 10 ns 1, 9 t chih test , nmi, int4:0, bclk1:0, t1:0in, ready, cts1:0 3ns1,9 t clis ad15:0 (ad7:0), ready 10 ns 1, 10 t clih ready, ad15:0 (ad7:0) 3 ns 1, 10 t clis hold, pereq, error 10 ns 1, 9 t clih hold, pereq, error 3ns1,9 notes: 1. see ac timing waveforms , for waveforms and definition. 2. measure at v ih for high time, v il for low time. 3. only required to guarantee i cc . maximum limits are bounded by t c ,t ch and t cl . 4. specified for a 50 pf load, see figure 13 for capacitive derating information. 5. specified for a 50 pf load, see figure 14 for rise and fall times outside 50 pf. 6. see figure 14 for rise and fall times. 7. t chov1 applies to bhe (rfsh ), lock and a19:16 only after a hold release. 8. t chov2 applies to rd and wr only after a hold release. 9. setup and hold are required to guarantee recognition. 10. setup and hold are required for proper operation. 29 80c186eb/80c188eb, 80l186eb/80l188eb ac specifications ac characteristicse80c186eb20/80c186eb13 symbol parameter 20 mhz 13 mhz units notes min max min max input clock t f clkin frequency 0 40 0 26 mhz 1 t c clkin period 25 % 38.5 % ns 1 t ch clkin high time 10 % 12 % ns 1, 2 t cl clkin low time 10 % 12 % ns 1, 2 t cr clkin rise time 1818ns1,3 t cf clkin fall time 1818ns1,3 output clock t cd clkin to clkout delay 0 17 0 23 ns 1, 4 t clkout period 2 * t c 2 * t c ns 1 t ph clkout high time (t/2) b 5 (t/2) a 5 (t/2) b 5 (t/2) a 5ns 1 t pl clkout low time (t/2) b 5 (t/2) a 5 (t/2) b 5 (t/2) a 5ns 1 t pr clkout rise time 1616ns1,5 t pf clkout fall time 1616ns1,5 output delays t chov1 ale, s2:0 , den , dt/r , 3 22 3 25 ns 1,4,6,7 bhe (rfsh ), lock , a19:16 t chov2 gcs0:7 , lcs , ucs , ncs , 3 27 3 30 ns 1,4,6,8 rd ,wr t clov1 bhe (rfsh ), den , lock , 3 22 3 25 ns 1,4,6 resout, hlda, t0out, t1out, a19:16 t clov2 rd ,wr , gcs7:0 , lcs , 3 27 3 30 ns 1,4,6 ucs , ad15:0 (ad7:0, a15:8), ncs , inta1:0 , s2:0 t chof rd ,wr , bhe (rfsh ), 025025ns1 dt/r , lock , s2:0 , a19:16 t clof den , ad15:0 (ad7:0, 0 25 0 25 ns 1 a15:8) 30 80c186eb/80c188eb, 80l186eb/80l188eb ac specifications ac characteristicse80c186eb20/80c186eb13 (continued) symbol parameter 20 mhz 13 mhz units notes min max min max synchronous inputs t chis test , nmi, int4:0, bclk1:0, t1:0in, 10 10 ns 1, 9 ready, cts1:0 , p2.6, p2.7 t chih test , nmi, int4:0, bclk1:0, t1:0in, 3 3 ns 1, 9 ready, cts1:0 t clis ad15:0 (ad7:0), ready 10 10 ns 1, 10 t clih ready, ad15:0 (ad7:0) 3 3 ns 1, 10 t clis hold, pereq, error 10 10 ns 1, 9 t clih hold, pereq, error 3 3 ns 1, 9 notes: 1. see ac timing waveforms , for waveforms and definition. 2. measure at v ih for high time, v il for low time. 3. only required to guarantee i cc . maximum limits are bounded by t c ,t ch and t cl . 4. specified for a 50 pf load, see figure 13 for capacitive derating information. 5. specified for a 50 pf load, see figure 14 for rise and fall times outside 50 pf. 6. see figure 14 for rise and fall times. 7. t chov1 applies to bhe (rfsh ), lock and a19:16 only after a hold release. 8. t chov2 applies to rd and wr only after a hold release. 9. setup and hold are required to guarantee recognition. 10. setup and hold are required for proper operation. 31 80c186eb/80c188eb, 80l186eb/80l188eb ac specifications ac characteristicse80l186eb16 symbol parameter 16 mhz units notes min max input clock t f clkin frequency 0 32 mhz 1 t c clkin period 31.25 % ns 1 t ch clkin high time 13 % ns 1, 2 t cl clkin low time 13 % ns 1, 2 t cr clkin rise time 1 8 ns 1, 3 t cf clkin fall time 1 8 ns 1, 3 output clock t cd clkin to clkout delay 0 30 ns 1, 4 t clkout period 2 * t c ns 1 t ph clkout high time (t/2) b 5 (t/2) a 5ns 1 t pl clkout low time (t/2) b 5 (t/2) a 5ns 1 t pr clkout rise time 1 9 ns 1, 5 t pf clkout fall time 1 9 ns 1, 5 output delays t chov1 dt/r , lock , a19:16, r fsh 3 22 ns 1,4,6,7 t chov2 gcs0:7 , lcs , ucs , ncs ,rd ,wr 3 27 ns 1,4,6,8 t chov3 bhe , den 325ns1,4 t chov4 ale 3 30 ns 1, 4 t chov5 s2:0 333ns1,4 t clov1 lock , resout, hlda, t0out, t1out, a19:16 3 22 ns 1, 4, 6 t clov2 rd ,wr , gcs7:0 , lcs , ucs , ncs , inta1:0 , ad15:0 3 27 ns 1, 4, 6 (ad7:0, a15:8) t chof rd ,wr , bhe (rfsh ), dt/r , lock , s2:0 , a19:16 0 25 ns 1 t clof den , ad15:0 (ad7:0, a15:8) 0 25 ns 1 t clov3 bhe , den 3 25 ns 1,4,6 t clov5 s2:0 3 33 ns 1,4,6 32 80c186eb/80c188eb, 80l186eb/80l188eb ac specifications ac characteristicse80l186eb16 (continued) symbol parameter 16 mhz units notes min max synchronous inputs t chis test , nmi, int4:0, bclk1:0, t1:0in, ready, cts1:0 , p2.6, p2.7 15 ns 1, 9 t chih test , nmi, int4:0, t1:0in, bclk1:0, ready, cts1:0 3ns1,9 t clis ad15:0 (ad7:0), ready 15 ns 1, 10 t clih ready, ad15:0 (ad7:0) 3 ns 1, 10 t clis hold 15 ns 1, 9 t clih hold 3 ns 1, 9 notes: 1. see ac timing waveforms , for waveforms and definition. 2. measure at v ih for high time, v il for low time. 3. only required to guarantee i cc . maximum limits are bounded by t c ,t ch and t cl . 4. specified for a 50 pf load, see figure 13 for capacitive derating information. 5. specified for a 50 pf load, see figure 14 for rise and fall times outside 50 pf. 6. see figure 14 for rise and fall times. 7. t chov1 applies to bhe (rfsh ), lock and a19:16 only after a hold release. 8. t chov2 applies to rd and wr only after a hold release. 9. setup and hold are required to guarantee recognition. 10. setup and hold are required for proper operation. 33 80c186eb/80c188eb, 80l186eb/80l188eb ac specifications (continued) relative timings (80c186eb25, 20, 13/80l186eb16, 13, 8) symbol parameter min max units notes relative timings t lhll ale rising to ale falling t b 15 ns t avll address valid to ale falling (/2 t b 10 ns t plll chip selects valid to ale falling (/2 t b 10 ns 1 t llax address hold from ale falling (/2 t b 10 ns t llwl ale falling to wr falling (/2 t b 15 ns 1 t llrl ale falling to rd falling (/2 t b 15 ns 1 t whlh wr rising to ale rising (/2 t b 10 ns 1 t afrl address float to rd falling 0 ns t rlrh rd falling to rd rising (2 * t) b 5ns2 t wlwh wr falling to wr rising (2 * t) b 5ns2 t rhav rd rising to address active t b 15 ns t whdx output data hold after wr rising t b 15 ns t whph wr rising to chip select rising (/2 t b 10 ns 1 t rhph rd rising to chip select rising (/2 t b 10 ns 1 t phpl cs inactive to cs active (/2 t b 10 ns 1 t ovrh once active to resin rising t ns 3 t rhox once hold from resin rising t ns 3 notes: 1. assumes equal loading on both pins. 2. can be extended using wait states. 3. not tested 36 80c186eb/80c188eb, 80l186eb/80l188eb ac specifications (continued) serial port mode 0 timings (80c186eb25, 20, 13/80l186eb16, 13, 8) symbol parameter min max unit notes t xlxl txd clock period t (n a 1) ns 1, 2 t xlxh txd clock low to clock high (n l 1) 2t b 35 2t a 35 ns 1 t xlxh txd clock low to clock high (n e 1) t b 35 t a 35 ns 1 t xhxl txd clock high to clock low (n l 1) (n b 1) t b 35 (n b 1) t a 35 ns 1, 2 t xhxl txd clock high to clock low (n e 1) t b 35 t a 35 ns 1 t qvxh rxd output data setup to txd clock high (n l 1) (n b 1) t b 35 ns 1, 2 t qvxh rxd output data setup to txd clock high (n e 1) t b 35 ns 1 t xhqx rxd output data hold after txd clock high (n l 1) 2t b 35 ns 1 t xhqx rxd output data hold after txd clock high (n e 1) t b 35 ns 1 t xhqz rxd output data float after last txd clock high t a 20 ns 1 t dvxh rxd input data setup to txd clock high t a 20 ns 1 t xhdx rxd input data hold after txd clock high 0 ns 1 notes: 1. see figure 12 for waveforms. 2. n is the value of the bxcmp register ignoring the iclk bit (i.e., iclk e 0). 37 80c186eb/80c188eb, 80l186eb/80l188eb ac test conditions the ac specifications are tested with the 50 pf load shown in figure 7. see the derating curves section to see how timings vary with load capacitance. specifications are measured at the v cc /2 crossing point, unless otherwise specified. see ac timing waveforms, for ac specification definitions, test pins, and illustrations. 272433 8 c l e 50 pf for all signals. figure 7. ac test load ac timing waveforms 272433 9 figure 8. input and output clock waveform 38 80c186eb/80c188eb, 80l186eb/80l188eb 272433 10 note: 20% v cc k float k 80% v cc figure 9. output delay and float waveform 272433 11 figure 10. input setup and hold 39 80c186eb/80c188eb, 80l186eb/80l188eb 272433 12 note: pin names in parentheses apply to 80c188eb/80l188eb figure 11. relative signal waveform 272433 13 figure 12. serial port mode 0 waveform 40 80c186eb/80c188eb, 80l186eb/80l188eb derating curves typical output delay variations versus load capacitance 272433 14 figure 13 typical rise and fall variations versus load capacitance 272433 15 figure 14 41 80c186eb/80c188eb, 80l186eb/80l188eb reset the processor will perform a reset operation any time the resin pin active. the resin pin is actually synchronized before it is presented internally, which means that the clock must be operating before a reset can take effect. from a power-on state, resin must be held active (low) in order to guarantee cor- rect initialization of the processor. failure to pro- vide resin while the device is powering up will result in unspecified operation of the device. figure 14 shows the correct reset sequence when first applying power to the processor. an external clock connected to clkin must not exceed the v cc threshold being applied to the processor. this is nor- mally not a problem if the clock driver is supplied with the same v cc that supplies the processor. when attaching a crystal to the device, resin must remain active until both v cc and clkout are stable (the length of time is application specific and de- pends on the startup characteristics of the crystal circuit). the resin pin is designed to operate cor- rectly using an rc reset circuit, but the designer must ensure that the ramp time for v cc is not so long that resin is never really sampled at a logic low level when v cc reaches minimum operating conditions. figure 16 shows the timing sequence when resin is applied after v cc is stable and the device has been operating. note that a reset will terminate all activity and return the processor to a known operat- ing state. any bus operation that is in progress at the time resin is asserted will terminate immediately (note that most control signals will be driven to their inactive state first before floating). while resin is active, bus signals lock , a19/ once , and a18:16 are configured as inputs and weakly held high by internal pullup transistors. only 19/once can be overdriven to a low and is used to enable once mode. forcing lock or a18:16 low at any time while resin is low is prohibited and will cause unspecified device operation. 42 80c186eb/80c188eb, 80l186eb/80l188eb figure 15. cold reset waveforms 272433 16 note: clkout synchronization occurs on the rising edge of resin . if resin is sampled high while clkout is high (solid line), then clkout will remain low for two clkin periods. if resin is sampled high while clkout is low (dashed line), then clkout will not be affected. pin names in parentheses apply to 80c188eb/80l188eb 43 80c186eb/80c188eb, 80l186eb/80l188eb figure 16. warm reset waveforms 272433 17 note: clkout synchronization occurs on the rising edge of resin . if resin is sampled high while clkout is high (solid line), then clkout will remain low for two clkin periods. if resin is sampled high while clkout is low (dashed line), then clkout will not be affected. pin names in parentheses apply to 80c188eb/80l188eb 44 80c186eb/80c188eb, 80l186eb/80l188eb bus cycle waveforms figures 17 through 23 present the various bus cy- cles that are generated by the processor. what is shown in the figure is the relationship of the various bus signals to clkout. these figures along with the information present in ac specifications allow the user to determine all the critical timing analysis needed for a given application. 272433 18 note: pin names in parentheses apply to 80c188eb/80l188eb figure 17. read, fetch, and refresh cycle waveforms 45 80c186eb/80c188eb, 80l186eb/80l188eb 272433 19 note: pin names in parentheses apply to 80c188eb/80l188eb figure 18. write cycle waveforms 46 80c186eb/80c188eb, 80l186eb/80l188eb 272433 20 note: the address driven is typically the location of the next instruction prefetch. under a majority of instruction sequences the ad15:0 (ad7:0) bus will float, while the a19:16 (a19:8) bus remains driven and all bus control signals are driven to their inactive state. pin names in parentheses apply to 80c188eb/80l188eb figure 19. halt cycle waveforms 47 80c186eb/80c188eb, 80l186eb/80l188eb 272433 21 note: pin names in parentheses apply to 80c188eb/80l188eb figure 20. interrupt acknowledge cycle waveform 48 80c186eb/80c188eb, 80l186eb/80l188eb 272433 22 note: pin names in parentheses apply to 80c188eb/80l188eb figure 21. hold/hlda waveforms 49 80c186eb/80c188eb, 80l186eb/80l188eb 272433 23 notes: 1. ready must be low by either edge to cause a wait state. 2. lighter lines indicate read cycles, darker lines indicate write cycles. pin names in parentheses apply to 80c188eb/80l188eb figure 22. refresh during hold acknowledge 50 80c186eb/80c188eb, 80l186eb/80l188eb 272433 24 notes: 1. ready must be low by either edge to cause a wait state. 2. lighter lines indicate read cycles, darker lines indicate write cycles. pin names in parentheses apply to 80c188eb/80l188eb figure 23. ready waveforms 51 80c186eb/80c188eb, 80l186eb/80l188eb execution timings a determination of program execution timing must consider the bus cycles necessary to prefetch in- structions as well as the number of execution unit cycles necessary to execute instructions. the fol- lowing instruction timings represent the minimum execution time in clock cycles for each instruction. the timings given are based on the following as- sumptions: # the opcode, along with any data or displacement required for execution of a particular instruction, has been prefetched and resides in the queue at the time it is needed. # no wait states or bus holds occur. # all word-data is located on even-address bound- aries (80c186eb only). all jumps and calls include the time required to fetch the opcode of the next instruction at the destination address. all instructions which involve memory accesses can require one or two additional clocks above the mini- mum timings shown due to the asynchronous hand- shake between the bus interface unit (biu) and exe- cution unit. with a 16-bit biu, the 80c186eb has sufficient bus performance to ensure that an adequate number of prefetched bytes will reside in the queue (6 bytes) most of the time. therefore, actual program execu- tion time will not be substantially greater than that derived from adding the instruction timings shown. the 80c188eb 8-bit biu is limited in its performance relative to the execution unit. a sufficient number of prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time. therefore, actual program execution time will be substantially greater than that derived from adding the instruction timings shown. 52 80c186eb/80c188eb, 80l186eb/80l188eb instruction set summary 80c186eb 80c188eb function format clock clock comments cycles cycles data transfer mov e move: register to register/memory 1000100w modreg r/m 2/12 2/12 * register/memory to register 1000101w modreg r/m 2/9 2/9 * immediate to register/memory 1100011w mod000 r/m data data if w e 1 12/13 12/13 8/16-bit immediate to register 1011w reg data data if w e 1 3/4 3/4 8/16-bit memory to accumulator 1010000w addr-low addr-high 8 8 * accumulator to memory 1010001w addr-low addr-high 9 9 * register/memory to segment register 10001110 mod0reg r/m 2/9 2/13 segment register to register/memory 10001100 mod0reg r/m 2/11 2/15 push e push: memory 11111111 mod110 r/m 16 20 register 01010 reg 10 14 segment register 000reg110 9 13 immediate 011010s0 data data if s e 01014 pusha e push all 01100000 36 68 pop e pop: memory 10001111 mod000 r/m 20 24 register 01011 reg 10 14 segment register 000reg111 (reg i 01) 8 12 popa e popall 01100001 51 83 xchg e exchange: register/memory with register 1000011w modreg r/m 4/17 4/17 * register with accumulator 10010 reg 3 3 in e input from: fixed port 1110010w port 10 10 * variable port 1110110w 8 8 * out e output to: fixed port 1110011w port 9 9 * variable port 1110111w 7 7 * xlat e translate byte to al 11010111 11 15 lea e load ea to register 10001101 modreg r/m 6 6 lds e load pointer to ds 11000101 modreg r/m (mod i 11) 18 26 les e load pointer to es 11000100 modreg r/m (mod i 11) 18 26 lahf e load ah with flags 10011111 2 2 sahf e store ah into flags 10011110 3 3 pushf e push flags 10011100 9 13 popf e pop flags 10011101 8 12 shaded areas indicate instructions not available in 8086/8088 microsystems. note: * clock cycles shown for byte transfers. for word operations, add 4 clock cycles for all memory transfers. 53 80c186eb/80c188eb, 80l186eb/80l188eb instruction set summary (continued) 80c186eb 80c188eb function format clock clock comments cycles cycles data transfer (continued) segment e segment override: cs 00101110 2 2 ss 00110110 2 2 ds 00111110 2 2 es 00100110 2 2 arithmetic add e add: reg/memory with register to either 000000dw modreg r/m 3/10 3/10 * immediate to register/memory 100000sw mod000 r/m data data if s w e 01 4/16 4/16 * immediate to accumulator 0000010w data data if w e 1 3/4 3/4 8/16-bit adc e add with carry: reg/memory with register to either 000100dw modreg r/m 3/10 3/10 * immediate to register/memory 100000sw mod010 r/m data data if s w e 01 4/16 4/16 * immediate to accumulator 0001010w data data if w e 1 3/4 3/4 8/16-bit inc e increment: register/memory 1111111w mod000 r/m 3/15 3/15 * register 01000 reg 3 3 sub e subtract: reg/memory and register to either 001010dw modreg r/m 3/10 3/10 * immediate from register/memory 100000sw mod101 r/m data data if s w e 01 4/16 4/16 * immediate from accumulator 0010110w data data if w e 1 3/4 3/4 8/16-bit sbb e subtract with borrow: reg/memory and register to either 000110dw modreg r/m 3/10 3/10 * immediate from register/memory 100000sw mod011 r/m data data if s w e 01 4/16 4/16 * immediate from accumulator 0001110w data data if w e 1 3/4 3/4 * 8/16-bit dec e decrement register/memory 1111111w mod001 r/m 3/15 3/15 * register 01001 reg 3 3 cmp e compare: register/memory with register 0011101w modreg r/m 3/10 3/10 * register with register/memory 0011100w modreg r/m 3/10 3/10 * immediate with register/memory 100000sw mod111 r/m data data if s w e 01 3/10 3/10 * immediate with accumulator 0011110w data data if w e 1 3/4 3/4 8/16-bit neg e change sign register/memory 1111011w mod011 r/m 3/10 3/10 * aaa e ascii adjust for add 00110111 8 8 daa e decimal adjust for add 00100111 4 4 aas e ascii adjust for subtract 00111111 7 7 das e decimal adjust for subtract 00101111 4 4 mul e multiply (unsigned): 1111011w mod100 r/m register-byte 2628 2628 register-word 3537 3537 memory-byte 3234 3234 memory-word 4143 4143 * shaded areas indicate instructions not available in 8086/8088 microsystems. note: * clock cycles shown for byte transfers. for word operations, add 4 clock cycles for all memory transfers. 54 80c186eb/80c188eb, 80l186eb/80l188eb instruction set summary (continued) 80c186eb 80c188eb function format clock clock comments cycles cycles arithmetic (continued) imul e integer multiply (signed): 1111011w mod101 r/m register-byte 2528 2528 register-word 3437 3437 memory-byte 3134 3134 memory-word 4043 4043 * imul e integer immediate multiply 011010s1 modreg r/m data data if s e 0 2225/ 2225/ (signed) 2932 2932 div e divide (unsigned): 1111011w mod110 r/m register-byte 29 29 register-word 38 38 memory-byte 35 35 memory-word 44 44 * idiv e integer divide (signed): 1111011w mod111 r/m register-byte 4452 4452 register-word 5361 5361 memory-byte 5058 5058 memory-word 5967 5967 * aam e ascii adjust for multiply 11010100 00001010 19 19 aad e ascii adjust for divide 11010101 00001010 15 15 cbw e convert byte to word 10011000 2 2 cwd e convert word to double word 10011001 4 4 logic shift/rotate instructions: register/memory by 1 1101000w modtttr/m 2/15 2/15 register/memory by cl 1101001w modtttr/m 5 a n/17 a n5 a n/17 a n register/memory by count 1100000w modtttr/m count 5 a n/17 a n5 a n/17 a n ttt instruction 000 rol 001 ror 010 rcl 011 rcr 1 0 0 shl/sal 101 shr 111 sar and e and: reg/memory and register to either 001000dw modreg r/m 3/10 3/10 * immediate to register/memory 1000000w mod100 r/m data data if w e 1 4/16 4/16 * immediate to accumulator 0010010w data data if w e 1 3/4 3/4 * 8/16-bit test e and function to flags, no result: register/memory and register 1000010w modreg r/m 3/10 3/10 * immediate data and register/memory 1111011w mod000 r/m data data if w e 1 4/10 4/10 * immediate data and accumulator 1010100w data data if w e 1 3/4 3/4 8/16-bit or e or: reg/memory and register to either 000010dw modreg r/m 3/10 3/10 * immediate to register/memory 1000000w mod001 r/m data data if w e 1 4/16 4/16 * immediate to accumulator 0000110w data data if w e 1 3/4 3/4 * 8/16-bit shaded areas indicate instructions not available in 8086/8088 microsystems. note: * clock cycles shown for byte transfers. for word operations, add 4 clock cycles for all memory transfers. 55 80c186eb/80c188eb, 80l186eb/80l188eb instruction set summary (continued) 80c186eb 80c188eb function format clock clock comments cycles cycles logic (continued) xor e exclusive or: reg/memory and register to either 001100dw modreg r/m 3/10 3/10 * immediate to register/memory 1000000w mod110 r/m data data if w e 1 4/16 4/16 * immediate to accumulator 0011010w data data if w e 1 3/4 3/4 8/16-bit not e invert register/memory 1111011w mod010 r/m 3/10 3/10 * string manipulation movs e move byte/word 1010010w 14 14 * cmps e compare byte/word 1010011w 22 22 * scas e scan byte/word 1010111w 15 15 * lods e load byte/wd to al/ax 1010110w 12 12 * stos e store byte/wd from al/ax 1010101w 10 10 * ins e input byte/wd from dx port 0110110w 14 14 outs e output byte/wd to dx port 0110111w 14 14 repeated by count in cx (rep/repe/repz/repne/repnz) movs e move string 11110010 1010010w 8 a 8n 8 a 8n * cmps e compare string 1111001z 1010011w 5 a 22n 5 a 22n * scas e scan string 1111001z 1010111w 5 a 15n 5 a 15n * lods e load string 11110010 1010110w 6 a 11n 6 a 11n * stos e store string 11110010 1010101w 6 a 9n 6 a 9n * ins e input string 11110010 0110110w 8 a 8n 8 a 8n * outs e output string 11110010 0110111w 8 a 8n 8 a 8n * control transfer call e call: direct within segment 11101000 disp-low disp-high 15 19 register/memory 11111111 mod010 r/m 13/19 17/27 indirect within segment direct intersegment 10011010 segment offset 23 31 segment selector indirect intersegment 11111111 mod011 r/m (mod i 11) 38 54 jmp e unconditional jump: short/long 11101011 disp-low 14 14 direct within segment 11101001 disp-low disp-high 14 14 register/memory 11111111 mod100 r/m 11/17 11/21 indirect within segment direct intersegment 11101010 segment offset 14 14 segment selector indirect intersegment 11111111 mod101 r/m (mod i 11) 26 34 shaded areas indicate instructions not available in 8086/8088 microsystems. note: * clock cycles shown for byte transfers. for word operations, add 4 clock cycles for all memory transfers. 56 80c186eb/80c188eb, 80l186eb/80l188eb instruction set summary (continued) 80c186eb 80c188eb function format clock clock comments cycles cycles control transfer (continued) ret e return from call: within segment 11000011 16 20 within seg adding immed to sp 11000010 data-low data-high 18 22 intersegment 11001011 22 30 intersegment adding immediate to sp 11001010 data-low data-high 25 33 je/jz e jump on equal/zero 01110100 disp 4/13 4/13 jmp not jl/jnge e jump on less/not greater or equal 01111100 disp 4/13 4/13 taken/jmp jle/jng e jump on less or equal/not greater 01111110 disp 4/13 4/13 taken jb/jnae e jump on below/not above or equal 01110010 disp 4/13 4/13 jbe/jna e jump on below or equal/not above 01110110 disp 4/13 4/13 jp/jpe e jump on parity/parity even 01111010 disp 4/13 4/13 jo e jump on overflow 01110 000 disp 4/13 4/13 js e jump on sign 01111000 disp 4/13 4/13 jne/jnz e jump on not equal/not zero 01110101 disp 4/13 4/13 jnl/jge e jump on not less/greater or equal 01111101 disp 4/13 4/13 jnle/jg e jump on not less or equal/greater 01111111 disp 4/13 4/13 jnb/jae e jump on not below/above or equal 01110011 disp 4/13 4/13 jnbe/ja e jump on not below or equal/above 01110111 disp 4/13 4/13 jnp/jpo e jump on not par/par odd 01111011 disp 4/13 4/13 jno e jump on not overflow 01110001 disp 4/13 4/13 jns e jump on not sign 01111001 disp 4/13 4/13 jcxz e jump on cx zero 11100011 disp 5/15 5/15 loop e loop cx times 11100010 disp 6/16 6/16 loop not loopz/loope e loop while zero/equal 11100001 disp 6/16 6/16 taken/loop loopnz/loopne e loop while not zero/equal 11100000 disp 6/16 6/16 taken enter e enter procedure 11001000 data-low data-high l l e 0 15 19 l e 1 25 29 l l 1 22 a 16(n b 1) 26 a 20(n b 1) leave e leave procedure 11001001 8 8 int e interrupt: type specified 11001101 type 47 47 type 3 11001100 45 45 if int. taken/ into e interrupt on overflow 11001110 48/4 48/4 if int. not taken iret e interrupt return 11001111 28 28 bound e detect value out of range 01100010 modreg r/m 3335 3335 shaded areas indicate instructions not available in 8086/8088 microsystems. note: * clock cycles shown for byte transfers. for word operations, add 4 clock cycles for all memory transfers. 57 80c186eb/80c188eb, 80l186eb/80l188eb instruction set summary (continued) 80c186eb 80c188eb function format clock clock comments cycles cycles processor control clc e clear carry 11111000 2 2 cmc e complement carry 11110101 2 2 stc e set carry 11111001 2 2 cld e clear direction 11111100 2 2 std e set direction 11111101 2 2 cli e clear interrupt 11111010 2 2 sti e set interrupt 11111011 2 2 hlt e halt 11110100 2 2 wait e wait 10011011 6 6 if test e 0 lock e bus lock prefix 11110000 2 2 nop e no operation 10010000 3 3 (ttt lll are opcode to processor extension) shaded areas indicate instructions not available in 8086/8088 microsystems. note: * clock cycles shown for byte transfers. for word operations, add 4 clock cycles for all memory transfers. footnotes the effective address (ea) of the memory operand is computed according to the mod and r/m fields: if mod e 11 then r/m is treated as a reg field if mod e 00 then disp e 0 * , disp-low and disp- high are absent if mod e 01 then disp e disp-low sign-ex- tended to 16-bits, disp-high is absent if mod e 10 then disp e disp-high: disp-low if r/m e 000 then ea e (bx) a (si) a disp if r/m e 001 then ea e (bx) a (di) a disp if r/m e 010 then ea e (bp) a (si) a disp if r/m e 011 then ea e (bp) a (di) a disp if r/m e 100 then ea e (si) a disp if r/m e 101 then ea e (di) a disp if r/m e 110 then ea e (bp) a disp * if r/m e 111 then ea e (bx) a disp disp follows 2nd byte of instruction (before data if required) * except if mod e 00 and r/m e 110 then ea e disp-high: disp-low. ea calculation time is 4 clock cycles for all modes, and is included in the execution times given whenev- er appropriate. segment override prefix 0 0 1 reg 1 1 0 reg is assigned according to the following: segment reg register 00 es 01 cs 10 ss 11 ds reg is assigned according to the following table: 16-bit (w e 1) 8-bit (w e 0) 000 ax 000 al 001 cx 001 cl 010 dx 010 dl 011 bx 011 bl 100 sp 100 ah 101 bp 101 ch 110 si 110 dh 111 di 111 bh the physical addresses of all operands addressed by the bp register are computed using the ss seg- ment register. the physical addresses of the desti- nation operands of the string primitive operations (those addressed by the di register) are computed using the es segment, which may not be overridden. 58 80c186eb/80c188eb, 80l186eb/80l188eb errata an 80c186eb/80l186eb with a stepid value of 0001h has the following known errata. a device with a stepid of 0001h can be visually identified by the presence of an ``a'' alpha character next to the fpo number. the fpo number location is shown in figures 4, 5 and 6. 1. a19/once is not latched by the rising edge of resin . a19/once must remain active (low) at all times to remain in the once mode. removing a19/once after resin is high will return all out- put pins to a driving state, however, the 80c186eb will remain in a reset state. 2. during interrupt acknowledge (inta) bus cycles, the bus controller will ignore the state of the ready pin if the previous bus cycle ignored the state of the ready pin. this errata can only oc- cur if the chip-select unit is being used. all active chip-selects must be programmed to use ready (rdy bit must be programmed to a 1) if wait- states are required for inta bus cycles. 3. clkout will transition off the rising edge of clkin rather than the falling edge of clkin. this does not affect any bus timings other than t cd . 4. resin has a hysterisis of only 130 mv. it is rec- ommended that resin be driven by a schmitt triggered device to avoid processor lockup during reset using an rc circuit. 5. sint1 will only go active for one clock period when a receive or transmit interrupt is pending (i.e., it does not remain active until the s1sts register is read). if sint1 is to be connected to any of the processor interrupt lines (int0 int4), then it must be latched by user logic. an 80c186eb/80l186eb with a stepid value of 0001h or 0002h has the following known errata. a device with a stepid of 0002h can be visually iden- tified by noting the presence of a ``b'', ``c'', ``d'', or ``e'' alpha character next to the fpo number. the fpo number location is shown in figures 4, 5 and 6. 1. an internal condition with the interrupt controller can cause no acknowledge cycle on the inta1 line in response to int1. this errata only occurs when interrupt 1 is configured in cascade mode and a higher priority interrupt exists. this errata will not occur consistantly, it is dependent on in- terrupt timing. revision history this data sheet replaces the following data sheets: 270803-004 80c186eb 270885-003 80c188eb 270921-003 80l186eb 270920-003 80l188eb 272311-001 sb80c188eb/sb80l188eb 272312-001 sb80c186eb/sb80l186eb 59 |
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